When serial communications are performed using a plurality of lanes between ports, a transmission circuit as a connecting port divides transmission data into the number of lanes, and transmits the divided data through each lane. The reception circuit as a connected port restores the data received through each lane.
FIG. 1 is a configuration of a conventional reception circuit.
A reception circuit 11 includes a lane block 21-m (m=0 through 7)) and a deskew processing unit 31.
In this specification, it is assumed that the number of lanes is eight and the lane m is connected to a lane block 21-m. 
A lane block 21-0 includes a DESerializer 41, a Gear-Box 42, a 10 bit boundary detection circuit 43, an elastic buffer 44, a clock frequency difference compensation pattern detection circuit 45, and an 8B10B conversion circuit 46.
Lane blocks 21-1 through 21-7 have the same configurations as the lane block 21-0.
The DESerializer 41 converts received 1-bit width serial data into 4-bit width parallel data (DATA—4BIT 51). In addition, it performs a clock recovery from the received serial data, and generates a reception clock (RX_CLOCK_DIVIDE—4, and RX_CLOCK_DIVIDE—10).
The RX_CLOCK_DIVIDE—4 is a ¼ frequency clock with respect to the serial data transfer speed, and the RX_CLOCK_DIVIDE—10 is a 1/10 frequency clock. For example, when the serial data transfer speed is 2.5 GT/s, RX_CLOCK_DIVIDE—4 is 625 MHz, and RX_CLOCK_DIVIDE—10 is 250 MHz.
The serial data transfer is performed using generally known 8B10B conversion data. In the 8B10B conversion, the transmission circuit converts 8-bit data (8b-code) into 10-bit data (10b-code) and transmits the converted data. The reception circuit restores 10b-code to 8b-code. The 10b-code is referred to as a symbol.
The Gear-Box 42 is a FIFO buffer in which 4-bit width DATA—4BIT 51 is written using an RX_CLOCK_DIVIDE—4 clock, and 10-bit width DATA—10BIT_UNALIGNMENT 52 is read using an RX_CLOCK_DIVIDE—10 clock.
The 10 bit boundary detection circuit 43 detects a boundary pattern, adjusts the DATA—10BIT_UNALIGNMENT 52 into 10-bit boundary data (DATA—10BIT_ALIGNMENT 53) in a 10b-code unit, and outputs the DATA—10BIT_ALIGNMENT 53 to the elastic buffer 44. The 10-bit boundary pattern is included in a training pattern to be transferred during the initialization of the serial bus.
A training pattern is configured by a plurality of symbols, and a transmission circuit transmits the training pattern through each lane with the same timing.
The elastic buffer 44 is a FIFO buffer for absorbing the clock frequency difference between connection devices. A write address is incremented by one in every cycle. A read address is normally incremented by one in every cycle, but is held, or incremented by one or two according to the signal from the clock frequency difference compensation pattern detection circuit 45 when a clock frequency difference compensation pattern is detected.
A clock frequency difference compensation pattern is configured by a plurality of symbols, and transmitted through each lane with the same timing during the initialization of the serial bus and in the normal operation.
The clock frequency difference compensation pattern detection circuit 45 outputs a signal for adjustment of the read address of the elastic buffer 44.
A clock frequency difference compensation pattern is periodically transmitted through a serial bus for compensation of the clock frequency difference between connection devices. For example, when a clock frequency tolerance between connection devices is within ±300 ppm, the transmission circuit transmits one clock frequency difference compensation pattern within 1666 cycles.
The 8B10B conversion circuit 46 converts a 10b-code (DATA—10BIT 54) into a 8b-code (DATA—8BIT 55).
The deskew processing unit 31 includes a deskew buffer 51-m (m=0 through 7) and a deskew pattern detection circuit 52.
A deskew buffer 51 is a FIFO buffer, and outputs restored data with the skew among the lanes adjusted based on the deskew pattern detection position.
However, it is not a simple FIFO buffer, but changes a read address when adjusting the deskew positions.
The deskew pattern detection circuit 52 detects the position of the deskew pattern from the data output from each lane, and outputs to the deskew buffer 51a signal for control of the read address to adjust the skew among the lanes.
A deskew pattern is included in the training pattern transferred during the initialization of the serial bus.
After the adjustment of the deskew position at the initialization of the serial bus, the deskew position is readjusted each time a clock frequency difference compensation pattern is periodically received. To allow the elastic buffer 44 of each lane to independently compensate for the clock frequency difference, the deskew processing unit 31 receives a clock frequency difference compensation information 56 from each lane and readjusts the deskew position.
Conventionally, a serial bus for a plurality of lanes has been used as a bus not largely affecting the performance by the latency of an IO bus etc.
When a serial bus for a plurality of lanes is adopted for a system bus of an information processing device of a large server etc., the latency of the reception circuit of the LSI loaded into the server largely affects the performance of the entire server.
However, the conventional reception circuit has the problem of latency because of two FIFO buffers (elastic buffer and deskew buffer) for the respective functions.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2005-159578    [Patent Document 2] Japanese Laid-open Patent Publication No. 2008-172657